RISC-reduced instruction set computer

                                      MCS-012 Computer organisation and assembly Language



RISC Machine Features

There is some controversy concerning what is or is not a RISC processor. The debate centers upon whether to classify a machine as RISC, as opposed to CISC, by architectural differences such as an abundance of registers or by performance measures such as performance of benchmark programs. In this section, we mention a number of architectural features commonly associated with RISC machines.
Small, Simpler Instruction Set and Few Addressing Modes
Small, simple and few are relative terms. Instruction set sizes are typically less than 150. Four or fewer addressing modes are common, although some processors have more.
Instruction set formats tend to be fixed in size, in contrast to variable length instruction formats of CISC machines. The number of these fixed-length formats is small, often on the order of two or three. This results in a faster (hard-wired) decoding.
Single-cycle operations allow the instructions to execute rapidly. Load-Store design dictates that only Load and Store instructions access memory. Ideally, these are the only instructions which take more than one machine cycle to execute.
Elimination of complex instructions eliminates the need for microcode.
Many Registers
Operations execute faster when the data is in a register. Thirty-two or more registers are common for RISC machines. Some have more. Hardware maintained sets of registers, called register windows, are organized in a circular queue, with a new set added to the tail of the queue and an older set removed from the head of the queue.
Levels of Memory
In addition to secondary memory, and a large number of registers, RISC processors include cache memory. Sometimes there is a separate cache memory for operations and operands. There may be separate buses to each cache.
Special-Purpose Architectures

RISC machines are often designed for a particular application or language or operating system. There are RISC machines for signal processing, symbolic processing, AI, image processing, scientific calculations, graphics processing, multiprocessing, and parallel processing. In addition. there are several general-purpose RISC machines on the market.




RISC (reduced instruction set computer) is a microprocessor that is designed to perform a smaller number of types of computer instructions so that it can operate at a higher speed (perform more millions of instructions per second, or MIPS). Since each instruction type that a computer must perform requires additional transistors and circuitry, a larger list or set of computer instructions tends to make the microprocessor more complicated and slower in operation.

The RISC concept has led to a more thoughtful design of the microprocessor.
 Among design considerations are how well an instruction can be mapped to the clock
 speed of the microprocessor (ideally, an instruction can be performed in one clock
 cycle); how "simple" an architecture is required; and how much work can be done by the microchip
 itself without resorting to software help


Besides performance improvement, some advantages of RISC and related design improvements are:

A new microprocessor can be developed and tested more quickly if one of its aims is to be less complicated.

Operating system and application programmers who use the microprocessor's instructions will find it easier to develop code with a smaller instruction set.

The simplicity of RISC allows more freedom to choose how to use the space on a microprocessor.

Higher-level language compilers produce more efficient code than formerly because they have always tended to use the smaller set of instructions to be found in a RISC computer.

After the introduction of RISC, any "full-set" instruction computer was said to use complex instruction set computing (CISC).



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